VHDL multiplexer using case statements

VHDL multiplexer using case statements

library IEEE;

entity multiplexer4_1 is
port (
      i0 : in std_logic;
      i1 : in std_logic;
      i2 : in std_logic;
      i3 : in std_logic;
     sel : in std_logic_vector(1 downto 0);
     bitout : out std_logic
end multiplexer4_1;

architecture Behavioral of multiplexer4_1 is

case sel is
  when "00" => bitout <= i0;
  when "01" => bitout <= i1;
  when "10" => bitout <= i2;
  when others => bitout <= i3;
end case;
end process;

end Behavioral;

The testbench code used for testing the code is given below:

  LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;

  ENTITY testbench IS
  END testbench;

  ARCHITECTURE behavior OF testbench IS
          SIGNAL i0,i1,i2,i3,bitout :  std_logic:='0';
          SIGNAL sel :  std_logic_vector(1 downto 0):="00";
    UUT : entity work.multiplexer4_1 port map(i0,i1,i2,i3,sel,bitout);

     tb : PROCESS
            sel <="00";
            wait for 2 ns;
            sel <="01";
            wait for 2 ns;
            sel <="10";
             wait for 2 ns;
             sel <="11";
              wait for 2 ns;
            --more input combinations can be given here.
     END PROCESS tb;


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